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          <h1 id="1-文件——智能PDF"><a href="#1-文件——智能PDF" class="headerlink" title="1. 文件——智能PDF"></a>1. 文件——智能PDF</h1><p><img src="https://img-blog.csdnimg.cn/20200407180042202.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3FxXzMwNDQ3MzE1,size_16,color_FFFFFF,t_70" alt="1"></p>
<h1 id="2-可选择导出当前工程或当前文档"><a href="#2-可选择导出当前工程或当前文档" class="headerlink" title="2.可选择导出当前工程或当前文档"></a>2.可选择导出当前工程或当前文档</h1><p><img src="https://img-blog.csdnimg.cn/20200407180206711.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3FxXzMwNDQ3MzE1,size_16,color_FFFFFF,t_70" alt="2"></p>
<h1 id="3-可选择是否导出BOOM表"><a href="#3-可选择是否导出BOOM表" class="headerlink" title="3. 可选择是否导出BOOM表"></a>3. 可选择是否导出BOOM表</h1><p><img src="https://img-blog.csdnimg.cn/20200407180254612.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3FxXzMwNDQ3MzE1,size_16,color_FFFFFF,t_70" alt="3"></p>
<h1 id="4-在Multilayer-Composite-Print位置处右击，可选择需要导出的文件"><a href="#4-在Multilayer-Composite-Print位置处右击，可选择需要导出的文件" class="headerlink" title="4.在Multilayer Composite Print位置处右击，可选择需要导出的文件"></a>4.在Multilayer Composite Print位置处右击，可选择需要导出的文件</h1><ul>
<li>这里我选择的是装配文件Create Assembly Drawings<br><img src="https://img-blog.csdnimg.cn/20200407180442217.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3FxXzMwNDQ3MzE1,size_16,color_FFFFFF,t_70" alt="4"></li>
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<h1 id="5-双击选项框，选择打印细节"><a href="#5-双击选项框，选择打印细节" class="headerlink" title="5.双击选项框，选择打印细节"></a>5.双击选项框，选择打印细节</h1><ul>
<li>在这里我选择装配文件，top层和bottom层都选择的是：丝印、板框和阻焊层<br><img src="https://img-blog.csdnimg.cn/20200407181115386.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3FxXzMwNDQ3MzE1,size_16,color_FFFFFF,t_70" alt="5"></li>
<li>bottom层选择让它镜像<br><img src="https://img-blog.csdnimg.cn/20200407181401443.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3FxXzMwNDQ3MzE1,size_16,color_FFFFFF,t_70" alt="6"></li>
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<h1 id="6-颜色选择"><a href="#6-颜色选择" class="headerlink" title="6.颜色选择"></a>6.颜色选择</h1><p><img src="https://img-blog.csdnimg.cn/20200407181447628.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3FxXzMwNDQ3MzE1,size_16,color_FFFFFF,t_70" alt="7"></p>
<h1 id="7-最后导出当前文件就OK了"><a href="#7-最后导出当前文件就OK了" class="headerlink" title="7.最后导出当前文件就OK了"></a>7.最后导出当前文件就OK了</h1>
      
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          <p>【名词解释及其功能】</p>
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<li>坐标文件：简单来讲就是你的元器件所在位置，一般在SMT贴片时需要用到</li>
<li>IPC网表：该文件输出后，板场可根据该文件检查PCB的通短路情况，为电路设计的正确性打上双保险</li>
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<h1 id="1-坐标文件"><a href="#1-坐标文件" class="headerlink" title="1. 坐标文件"></a>1. 坐标文件</h1><h2 id="文件——装配输出——Generates-pick-and-place-files"><a href="#文件——装配输出——Generates-pick-and-place-files" class="headerlink" title="文件——装配输出——Generates pick and place files"></a>文件——装配输出——Generates pick and place files</h2><p><img src="https://img-blog.csdnimg.cn/20200407162654400.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3FxXzMwNDQ3MzE1,size_16,color_FFFFFF,t_70" alt="1"></p>
<h2 id="点击确定，即可输出"><a href="#点击确定，即可输出" class="headerlink" title="点击确定，即可输出"></a>点击确定，即可输出</h2><p><img src="https://img-blog.csdnimg.cn/20200407162917290.PNG?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3FxXzMwNDQ3MzE1,size_16,color_FFFFFF,t_70" alt="2"></p>
<h1 id="2-IPC网表输出"><a href="#2-IPC网表输出" class="headerlink" title="2. IPC网表输出"></a>2. IPC网表输出</h1><h2 id="文件——制造输出——Test-Point-Report"><a href="#文件——制造输出——Test-Point-Report" class="headerlink" title="文件——制造输出——Test Point Report"></a>文件——制造输出——Test Point Report</h2><p><img src="https://img-blog.csdnimg.cn/20200407163057316.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3FxXzMwNDQ3MzE1,size_16,color_FFFFFF,t_70" alt="3"></p>
<h2 id="选择IPC项，点击确认，即可输出"><a href="#选择IPC项，点击确认，即可输出" class="headerlink" title="选择IPC项，点击确认，即可输出"></a>选择IPC项，点击确认，即可输出</h2><p><img src="https://img-blog.csdnimg.cn/2020040716314023.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3FxXzMwNDQ3MzE1,size_16,color_FFFFFF,t_70" alt="4"><br>至此，坐标文件及网表已在工程文件夹下<br><img src="https://img-blog.csdnimg.cn/20200407163254669.png" alt="5"></p>

      
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          <p>我们在画好PCB后，需要将PCB输出为Gerber文件，并将文件交付板场，做出我们画的板子。接下来就讲讲怎样输出Gerber文件</p>
<h1 id="1-文件——制造输出——Gerber-Files"><a href="#1-文件——制造输出——Gerber-Files" class="headerlink" title="1.文件——制造输出——Gerber Files"></a>1.文件——制造输出——Gerber Files</h1><p><img src="https://img-blog.csdnimg.cn/20200407121052800.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3FxXzMwNDQ3MzE1,size_16,color_FFFFFF,t_70" alt="1"></p>
<h1 id="2-Gerber设置"><a href="#2-Gerber设置" class="headerlink" title="2.Gerber设置"></a>2.Gerber设置</h1><h2 id="层设置"><a href="#层设置" class="headerlink" title="层设置"></a>层设置</h2><ul>
<li>绘制层：选择使用的   	</li>
<li>镜像层：全部去掉<br><img src="https://img-blog.csdnimg.cn/20200407121202767.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3FxXzMwNDQ3MzE1,size_16,color_FFFFFF,t_70" alt="2"><br><img src="https://img-blog.csdnimg.cn/20200407121221693.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3FxXzMwNDQ3MzE1,size_16,color_FFFFFF,t_70" alt="3"></li>
</ul>
<h2 id="钻孔图层"><a href="#钻孔图层" class="headerlink" title="钻孔图层"></a>钻孔图层</h2><ul>
<li>钻孔图：输出所有使用的钻孔对</li>
<li>钻孔向导图：输出所有使用的钻孔对<br><img src="https://img-blog.csdnimg.cn/20200407121425392.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3FxXzMwNDQ3MzE1,size_16,color_FFFFFF,t_70" alt="4"></li>
</ul>
<h1 id="3-文件——制造输出——NC-Drill-Files"><a href="#3-文件——制造输出——NC-Drill-Files" class="headerlink" title="3. 	文件——制造输出——NC Drill Files"></a>3. 	文件——制造输出——NC Drill Files</h1><ul>
<li>直接点确定<br><img src="https://img-blog.csdnimg.cn/20200407121625333.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3FxXzMwNDQ3MzE1,size_16,color_FFFFFF,t_70" alt="5"><br><img src="https://img-blog.csdnimg.cn/20200407121707780.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3FxXzMwNDQ3MzE1,size_16,color_FFFFFF,t_70" alt="6"></li>
</ul>
<h1 id="至此输出的文件已在你所在的工程目录下，可以将文件交付板场了"><a href="#至此输出的文件已在你所在的工程目录下，可以将文件交付板场了" class="headerlink" title="至此输出的文件已在你所在的工程目录下，可以将文件交付板场了"></a>至此输出的文件已在你所在的工程目录下，可以将文件交付板场了</h1><p><img src="https://img-blog.csdnimg.cn/20200407121901477.png" alt="7"></p>

      
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          <h2 id="一、逻辑值"><a href="#一、逻辑值" class="headerlink" title="一、逻辑值"></a>一、逻辑值</h2><p>Verilog中变量只有四种状态</p>
<ol>
<li>0低电平</li>
<li>1高电平</li>
<li>X表示未知(但存在)</li>
<li>Z表示悬空状态(未知就真的是未知)</li>
</ol>
<h2 id="二、数字进制格式"><a href="#二、数字进制格式" class="headerlink" title="二、数字进制格式"></a>二、数字进制格式</h2><figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br></pre></td><td class="code"><pre><span class="line"><span class="number">4&#x27;b0101</span></span><br><span class="line"><span class="number">4&#x27;d2</span>			<span class="comment">//4表示2进制数的位宽</span></span><br><span class="line"><span class="number">4&#x27;ha</span>			<span class="comment">//若没有指定位宽，则默认为32位(2进制)数据</span></span><br><span class="line"><span class="number">16&#x27;b1001_1010_1010_1001</span>=<span class="number">16&#x27;h9aa9</span></span><br></pre></td></tr></table></figure>

<h2 id="三、标识符-类似C语言变量名"><a href="#三、标识符-类似C语言变量名" class="headerlink" title="三、标识符(类似C语言变量名)"></a>三、标识符(类似C语言变量名)</h2><ol>
<li>标识符可以是任意一组字母、数字、$符号和下划线的组合</li>
<li>标识符第一个字符必须是字母或者下划线</li>
<li>标识符是区分大小写的</li>
<li>建议普通内部信号全部小写</li>
</ol>
<h2 id="四、数据类型"><a href="#四、数据类型" class="headerlink" title="四、数据类型"></a>四、数据类型</h2><p>Verilog中数据类型有：<em>寄存器类型、线网类型、参数类型</em>。真正在数字电路中起作用的数据类型应该是<strong>寄存器数据类型</strong>和<strong>线网数据类型</strong>，因为这两个数据类型可以直接映射在电路中</p>
<h4 id="寄存器类型"><a href="#寄存器类型" class="headerlink" title="寄存器类型"></a>寄存器类型</h4><ol>
<li>表示一个抽象的数据存储单元，关键字为reg，初始值为不确定值X<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br></pre></td><td class="code"><pre><span class="line">reg [31:0] delay_cnt;	// [31:0] 为位宽，不表明则默认为位宽1，不可赋初值。</span><br></pre></td></tr></table></figure></li>
<li>reg类型的数据只能在always语句和initial语句中被赋值</li>
<li>如果always中带有时钟信号，则该寄存器变量对应为触发器，如果always中没有时钟信号，则该寄存器为硬件连线</li>
</ol>
<h4 id="线网类型"><a href="#线网类型" class="headerlink" title="线网类型"></a>线网类型</h4><blockquote>
<p>线网类型包括wire和tri型，他们有什么区别呢？ 	<br>线网数据类型包括wire和tri等，wire最常见，不必多说，很多情况下直接声明为wire即可。<br>至于tri其实和wire在用法上是一模一样的，不过有时候，我们需要定义一些会被三态门驱动的硬件连线，用tri来命名会让代码更具有可读性，让人一看就知道这根连线上会出现Z状态，仅此而已！<br>回答来自：<a target="_blank" rel="noopener" href="http://www.openedv.com/forum.php?mod=viewthread&tid=286442&extra=page=1">正点原子开源电子论坛</a></p>
</blockquote>
<ol>
<li>表示结构实体(例如门)之间的物力连线</li>
<li>变量不能存储值，它的值是由驱动它的元件所决定的，驱动线网变量的元件有：门、连续赋值语句、assign等</li>
<li>若无驱动原件连在线网类型，则为高阻态</li>
<li>位宽和reg定义一样</li>
</ol>
<h4 id="参数类型-类似于C语言的define"><a href="#参数类型-类似于C语言的define" class="headerlink" title="参数类型(类似于C语言的define)"></a>参数类型(类似于C语言的define)</h4><ol>
<li>实际就是一个常量，用parameter定义<br><code>parameter H_SYNC = 11&#39;d41</code></li>
<li>参数类型数据定义状态机的状态、数据位宽、延时大小。可通过参数传递改变被调用模块已定义的函数，类似C语言的调用函数对模块赋值</li>
</ol>
<h2 id="五、运算符"><a href="#五、运算符" class="headerlink" title="五、运算符"></a>五、运算符</h2><ol>
<li><p>算数运算符<br>加减乘除法只能实现整数运算（+、-、*、&#x2F;）<br>%(a%b即取模)</p>
</li>
<li><p>关系运算符<br><code>&lt;=    &gt;=    等C语言中的比较运算符</code></p>
</li>
<li><p>逻辑运算符<br><code>! &amp;&amp; ||逻辑与或操作</code></p>
</li>
<li><p>条件运算符<br>Verilog中条件运算符就一个</p>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br></pre></td><td class="code"><pre><span class="line">?  :</span><br><span class="line">a?b:c</span><br></pre></td></tr></table></figure></li>
<li><p>位运算符<br>对每一位进行操作<br>不同位宽，小位宽变量高位补零再运算<br><code> ~、&amp;、|、^</code></p>
</li>
<li><p>移位运算符<br>空位补零</p>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br></pre></td><td class="code"><pre><span class="line">4&#x27;b1001&lt;&lt; 2 = 6&#x27;b100100;	//左移位宽增加</span><br><span class="line">4&#x27;b1001&gt;&gt; 1 = 4&#x27;b0100;		//右移位宽不变</span><br></pre></td></tr></table></figure>
</li>
<li><p>拼接运算符</p>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br></pre></td><td class="code"><pre><span class="line">&#123; , &#125;:</span><br><span class="line">&#123;a,b&#125;				//将a和b拼接起来作为一个新信号</span><br><span class="line">c=&#123;a,b[3:0]&#125;;		//a、b均为8位，则是将8位a和b的第3到第0位拼在一起，结果是c[11:0]</span><br></pre></td></tr></table></figure>
<p>学习视频：<a target="_blank" rel="noopener" href="https://www.bilibili.com/video/BV194411f7GD?p=12">正点原子FPGA系列教程Verilog语法篇</a></p>
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          <h2 id="一、结构语句"><a href="#一、结构语句" class="headerlink" title="一、结构语句"></a>一、结构语句</h2><h4 id="initial和always"><a href="#initial和always" class="headerlink" title="initial和always"></a>initial和always</h4><ul>
<li>两语句后紧跟的都是过程块(顺序块)语句</li>
</ul>
<ol>
<li>initial语句在模块中只执行一次，常用于测试文件的编写，用来产生仿真测试信号(激励信号)，或者用于对存储器变量赋初值</li>
</ol>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br></pre></td><td class="code"><pre><span class="line">initial begin</span><br><span class="line">    _sys_clk      &lt;=1&#x27;b0;</span><br><span class="line">    _sys_rst_n    &lt;=1&#x27;b0;</span><br><span class="line">    _touch_key    &lt;=1&#x27;b0;</span><br><span class="line">    #20 sys_rst_n &lt;=1&#x27;b1;</span><br><span class="line">    #10 touch_key &lt;=1&#x27;b1;</span><br><span class="line">    #30 touch_key &lt;=1&#x27;b0;</span><br><span class="line">    #110touch_key &lt;=1&#x27;b1;</span><br><span class="line">    #30 touch_key &lt;=1&#x27;b0;</span><br><span class="line">end</span><br></pre></td></tr></table></figure>

<ol start="2">
<li>always语句一直在不断地重复活动，但是只有和一定的时间控制结合在一起才有作用</li>
</ol>
<ul>
<li>always的时间控制可以是沿触发，也可以是电平触发。<strong>沿触发的always块常常描述时许逻辑行为，电平触发的描述常常描述组合逻辑行为</strong></li>
</ul>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br></pre></td><td class="code"><pre><span class="line">always @( * ) begin     //表示对后面语句块中所有输入变量的变化都是敏感的</span><br></pre></td></tr></table></figure>

<blockquote>
<p><strong>组合逻辑电路</strong>中，任意时刻的输出仅仅取决于该时刻的输入，与电路原来的状态无关。<br><strong>时许逻辑电路</strong>中，任意时刻的输出不仅取决于当时的输入信号，而且还取决于电路原来的状态。或者说还与以前的输入有关，因此时许逻辑必须具备记忆功能。</p>
</blockquote>
<h2 id="二、赋值语句"><a href="#二、赋值语句" class="headerlink" title="二、赋值语句"></a>二、赋值语句</h2><ul>
<li><strong>不允许在多个always块中对同一个变量进行赋值！</strong></li>
</ul>
<ol>
<li>阻塞赋值(可看作一个步骤)</li>
</ol>
<ul>
<li>计算RHS并更新LHS</li>
<li>一条语句执行完再执行下一条语句</li>
</ul>
<ol start="2">
<li>非阻塞赋值</li>
</ol>
<ul>
<li>赋值开始，计算RHS</li>
<li>赋值结束，更新LHS</li>
<li>非阻塞赋值只能用于对寄存器类型的变量进行赋值，因此<strong>只能在initial块和always块等过程块中</strong></li>
</ul>
<h2 id="三、条件语句"><a href="#三、条件语句" class="headerlink" title="三、条件语句"></a>三、条件语句</h2><ol>
<li>if_else语句(与C语言相同)</li>
</ol>
<ul>
<li>条件语句必须在过程块中使用</li>
<li>允许一定形式的简写</li>
</ul>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br></pre></td><td class="code"><pre><span class="line">if(a)等同于if(a==1)</span><br><span class="line">if(!a)等同于if(a!=1)</span><br></pre></td></tr></table></figure>

<ul>
<li>允许嵌套</li>
</ul>
<ol start="2">
<li>case语句</li>
</ol>
<ul>
<li>所有表达式位宽要相等：不能用’bx来代替n’bx</li>
</ul>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br></pre></td><td class="code"><pre><span class="line">case (num)</span><br><span class="line">    4&#x27;h0 :    seg_led &lt;= 8&#x27;b1100_0000;</span><br><span class="line">    default : seg_led &lt;= 8&#x27;b1100_0000;</span><br></pre></td></tr></table></figure>

<ul>
<li>casez表示不考虑表达式中的高阻值，要考虑x</li>
<li>casex不考虑高阻值z 和 不定值x</li>
</ul>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br></pre></td><td class="code"><pre><span class="line">reg [7:0] sel;</span><br><span class="line">casez(sel)</span><br><span class="line">    8&#x27; b1100_zzzz;</span><br><span class="line">    8&#x27; b1100_xxzz;</span><br></pre></td></tr></table></figure>


      
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          <h2 id="一、显示函数"><a href="#一、显示函数" class="headerlink" title="一、显示函数"></a>一、显示函数</h2><ol>
<li>$display(“带格式字符串”,参数1,参数2,…);</li>
</ol>
<ul>
<li>在文本后会加一个<strong>换行</strong></li>
</ul>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br></pre></td><td class="code"><pre><span class="line">module sdispl;</span><br><span class="line">	interger i;		//i为整型</span><br><span class="line">	reg [3:0] x;	//x为4位</span><br><span class="line">	initial begin	//initial块，只执行一次</span><br><span class="line">	i=21;			</span><br><span class="line">	x=4&#x27;he;</span><br><span class="line">	$display(&quot;1\t%d\n2\t%h\\&quot;,i, x);//输出显示</span><br><span class="line">	end </span><br><span class="line">endmodule	</span><br></pre></td></tr></table></figure>
<p><img src="https://img-blog.csdnimg.cn/20200624103639699.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3FxXzMwNDQ3MzE1,size_16,color_FFFFFF,t_70" alt="在这里插入图片描述"></p>
<ol start="2">
<li>$write(“带格式字符串”,参数1,参数2,…);</li>
</ol>
<ul>
<li>在文本后<strong>不会</strong>加换行</li>
</ul>
<ol start="3">
<li>$strobe和$monltor</li>
</ol>
<ul>
<li>$strobe  (“带格式字符串”,参数1,参数2,…);</li>
<li>$monitor(“带格式字符串”,参数1,参数2,…);</li>
</ul>
<h2 id="二、停止函数"><a href="#二、停止函数" class="headerlink" title="二、停止函数"></a>二、停止函数</h2><ol>
<li>$finish表示停止仿真</li>
<li>$stop表示暂停仿真</li>
</ol>
<h2 id="三、系统时间函数"><a href="#三、系统时间函数" class="headerlink" title="三、系统时间函数"></a>三、系统时间函数</h2><ol>
<li>$time返回一个64位整数时间值</li>
<li>$stime返回一个32位整数时间值</li>
<li>$realtime返回一个实数时间值</li>
<li>$timeformat控制时间的显示方式</li>
</ol>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br></pre></td><td class="code"><pre><span class="line">示例代码</span><br><span class="line">$monitor(&quot;%d d=%b,e=%b&quot;,$stime,d,e);</span><br></pre></td></tr></table></figure>

<h2 id="四、文件操作"><a href="#四、文件操作" class="headerlink" title="四、文件操作"></a>四、文件操作</h2><figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br></pre></td><td class="code"><pre><span class="line">文件句柄=$fopen(&quot;文件名&quot;)					//打开文件</span><br><span class="line">$fstrobe(文件句柄,&quot;带格式字符串&quot;,参数列表)   //strobe到文件，$fdisplay语句格式与它相同</span><br><span class="line">$monitor可以多个进程同时进行</span><br><span class="line">$fclose(文件);						   //关闭文件</span><br><span class="line">$feof(文件);							   //检查是否到文件末尾</span><br></pre></td></tr></table></figure>



      
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          <h2 id="一、Verilog注释"><a href="#一、Verilog注释" class="headerlink" title="一、Verilog注释"></a>一、Verilog注释</h2><p>两种注释方式</p>
<blockquote>
<p>&#x2F;&#x2F;<br>&#x2F;*     *&#x2F;</p>
</blockquote>
<h2 id="二、Verilog关键字"><a href="#二、Verilog关键字" class="headerlink" title="二、Verilog关键字"></a>二、Verilog关键字</h2><p>变量定义不可以和关键字重合</p>
<h2 id="三、Verilog程序框架"><a href="#三、Verilog程序框架" class="headerlink" title="三、Verilog程序框架"></a>三、Verilog程序框架</h2><ul>
<li>基本设计单元是模块，模块由两部分组成，一部分描述<strong>接口</strong>，另一部分描述<strong>逻辑功能</strong></li>
<li>每个Verilog程序包括4个主要部分：端口定义、IO说明、内部信号声明、功能定义<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br></pre></td><td class="code"><pre><span class="line">module block(a,b,c,d);      //端口定义</span><br><span class="line">    input a,b;              //IO说明  </span><br><span class="line">    output c,d;</span><br><span class="line">    assign c = a | b;</span><br><span class="line">    assign d = a &amp; b;</span><br><span class="line">endmodule</span><br></pre></td></tr></table></figure></li>
</ul>
<h4 id="功能定义部分的三种方法-并行"><a href="#功能定义部分的三种方法-并行" class="headerlink" title="功能定义部分的三种方法(并行)"></a>功能定义部分的三种方法(并行)</h4><ul>
<li><strong>并行</strong>即模块同时开始执行，并无先后顺序</li>
</ul>
<ol>
<li>assign语句(描述组合逻辑)</li>
<li>always语句(组合&#x2F;时许逻辑)</li>
<li>例化实例元件<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br></pre></td><td class="code"><pre><span class="line">and #2 u1(q,a,b);</span><br></pre></td></tr></table></figure></li>
</ol>
<h4 id="模块的调用"><a href="#模块的调用" class="headerlink" title="模块的调用"></a>模块的调用</h4><ul>
<li>在模块调用时，信号通过模块端口在模块之间传递</li>
<li><strong>模块的输入可为wire、reg型，但输出必须为wire型</strong></li>
<li>模块调用位宽必须保持一致</li>
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          <h2 id="一、状态机概念-State-Machine"><a href="#一、状态机概念-State-Machine" class="headerlink" title="一、状态机概念(State Machine)"></a>一、状态机概念(State Machine)</h2><ul>
<li>有限状态机(Finite State Machine,简称FSM)：在有限个状态之间按一定规律转换的时序电路</li>
</ul>
<h2 id="二、状态机模型"><a href="#二、状态机模型" class="headerlink" title="二、状态机模型"></a>二、状态机模型</h2><ul>
<li>模型由三个部分组成：产生下一状态的组合逻辑<strong>F</strong>、状态寄存器、产生输出的组合逻辑<strong>G</strong></li>
</ul>
<ol>
<li><strong>状态寄存器</strong>由一组触发器组成，用来记忆状态机当前所处的状态，状态的改变只发生在时钟的跳变沿</li>
<li>状态是否改变、如何改变，取决于组合逻辑F的输出，F是当前状态和输入信号的函数</li>
<li>状态机的输出由组合逻辑G提供，G是当前状态和输入信号的函数</li>
</ol>
<ul>
<li>Mealy状态机与Moore状态机，Moore状态机是Mealy状态机的一个特例。Moore状态机只与当前的状态有关，而与输入信号无关</li>
</ul>
<h2 id="三、状态机设计"><a href="#三、状态机设计" class="headerlink" title="三、状态机设计"></a>三、状态机设计</h2><h4 id="常规状态机"><a href="#常规状态机" class="headerlink" title="常规状态机"></a>常规状态机</h4><ul>
<li>状态机四段论：状态空间定义、状态跳转、下一个状态判断、各个状态下的动作</li>
</ul>
<ol>
<li>状态空间</li>
</ol>
<ul>
<li><strong>所有状态的集合为状态空间</strong>，对每个状态编码</li>
</ul>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br></pre></td><td class="code"><pre><span class="line">//独热码：每个状态只有一个寄存器置位，译码逻辑简单</span><br><span class="line">parameter APPLE    =   4&#x27;b1000;</span><br><span class="line">parameter ORANGE   =   4&#x27;b0100;</span><br><span class="line">parameter BANANA   =   4&#x27;b0010;</span><br><span class="line">parameter CHERRY   =   4&#x27;b0001;</span><br></pre></td></tr></table></figure>

<ol start="2">
<li>状态跳转(时序逻辑)</li>
</ol>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br></pre></td><td class="code"><pre><span class="line">always @(posedge clk or negedge rst_n)  begin</span><br></pre></td></tr></table></figure>

<ol start="3">
<li>下一个状态的判断(组合逻辑)</li>
</ol>
<ul>
<li>用case语句判断当前状态，使用阻塞赋值</li>
<li>if&#x2F;else要配对，避免latch(锁存器)的产生</li>
</ul>
<ol start="4">
<li>各个状态下的动作</li>
</ol>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br></pre></td><td class="code"><pre><span class="line">//简单情况</span><br><span class="line">wire read_book;</span><br><span class="line">assign read_bool = (currentn_state == STUDY) ? 1&#x27;b1 : 1&#x27;b0</span><br><span class="line">//若状态描述较复杂</span><br><span class="line">always @ (currentn_state) begin</span><br><span class="line">    if(currentn_state == STUDY)</span><br><span class="line">        read_book = 1;</span><br><span class="line">    else</span><br><span class="line">        read_book = 0;</span><br><span class="line">end</span><br></pre></td></tr></table></figure>

<h4 id="三段式状态机"><a href="#三段式状态机" class="headerlink" title="三段式状态机"></a>三段式状态机</h4><p>可以在组合逻辑后再增加一级寄存器来实现时序逻辑输出：</p>
<ol>
<li>可以有效滤去组合逻辑输出的毛刺</li>
<li>进行时序计算和约束</li>
<li>对于总线形式的输出信号来说，容易使总线数据对齐，从而减小总线数据间的偏移，减小接收端数据采样出错的频率</li>
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          <h2 id="【学习笔记】STM32前期学习的一些知识点总结"><a href="#【学习笔记】STM32前期学习的一些知识点总结" class="headerlink" title="【学习笔记】STM32前期学习的一些知识点总结"></a>【学习笔记】STM32前期学习的一些知识点总结</h2><p>在2019年的8月，一个月入门STM32，仍然记得每天在实验室埋头苦干的日子。最近翻出来当时的暑假学习总结文档，与大家分享分享。论述如有错误，望大家指正。</p>
<p><strong>1. CPU时钟如何产生？</strong><br>由晶体振荡器产生的，俗称晶振。之所以晶振能当作振荡器使用是因为它具有“压电效应”。在晶振两端加上电场，晶振会产生机械变形，若加上交变电场就能产生机械振动。</p>
<p><strong>2. 时钟定时器（TIM）的周期（或者频率）怎么确定？计算公式是什么？<br>定时器的时钟来源于APB1和APB2的一个倍频器，定时器的周期公式为</strong></p>
<blockquote>
<p>T&#x3D;（arr+1）*(PSC+1)&#x2F;Tck  </p>
</blockquote>
<p>其中TCK为时钟频率，时钟频率可以直接由晶振产生，也可以用PLL电路对晶振频率倍频或分频产生。PSC为时钟预分频系数，arr为自动重装载值。这两个值可以自己设置，从而设置定时器的定时时间。</p>
<p><strong>3.	PWM是什么？举例说明它有什么作用。</strong><br>PWM是脉冲宽度调制技术，通过调节高低电平的占空比来输出，来等效地获得所需要波形，从而输出不同大小的等效电流。灯的亮度，电机转动速度等均可以用PWM控制。</p>
<p><strong>4.	寄存器、RAM、ROM（Flash）有什么区别？</strong><br>寄存器是CPU的内部组成部分，它们可以暂存指令、数据、地址。我们配置库函数实现各种功能的本质是对寄存器操作，向其发送指令，缓存数据等。<br>RAM也叫内存，它分为静态RAM（SRAM）和动态RAM（DRAM）。SRAM速度非常快，不需要刷新电路就能保存数据，是目前最快的存储设备。DRAM保存数据的时间很短，它需要内存刷新电路，每隔一段时间刷新充电一次。<br>注：刷新涉及到内存工作原理，一个DRAM存储单元是0还是1取决于电容是否有电荷，有电荷表示1，无电荷表示0。代表1的电容会放电，代表0的电容会吸收电荷，这就是数据丢失的原因；刷新操作定期对电容进行检查，若电量大于满电量的1／2，则认为其代表1，并把电容充满电；若电量小于1／2，则认为其代表0，并把电容放电，藉此来保持数据的连续性。<br>ROM是只读存储器，一旦储存资料就无法再将之改变或删除，后来发展出来了可编程只读存储器（PROM），可擦可编程只读存储器（EPROM）和电子式可擦除可编程只读存储器（EEPROM）<br>FLASH就是闪存，属于内存器件的一种，不仅具备EEPROM的性能，且掉电不会丢失数据。</p>
<p><strong>5.	看门狗有什么作用？它的原理是什么？</strong><br>看门狗是一种用于监测单片机程序运行状态的模块或者芯片。作用是：当程序执行异常，看门狗发送复位信号，使程序重新执行。本质是计数器从设定值计数到0时，看门狗发送复位信号。当程序正常运行时，在计数器减到0前“喂狗”，即使计数值回到设定值，使得看门狗始终不发送复位信号。当程序异常时，无法“喂狗”，则计数器到0时，“狗叫”，发送复位信号，程序重新执行。</p>
<p><strong>6.	在调用函数、进入中断时会压栈。简述一下压栈？</strong><br>栈又名堆栈，它是存储的系统。可以把栈理解为弹夹，压栈就是压子弹，写入数据；出栈是发射子弹，输出数据。这样的顺序满足：先进后出，后进先出。</p>
<p><strong>7.	内存分为哪几个区？栈区、堆区、全局变量区中分别存储哪些数据？</strong><br>内存分为：代码区(code area)、全局变量区(data area)、栈区(stack area)、堆区(heap area)。</p>
<ol>
<li>栈区存放函数的参数值、局部变量的值。</li>
<li>堆是由程序员自己申请并指明大小，栈区能存放的数据它也能存放。</li>
<li>全局变量区存放全局变量、静态数据、const常量，程序结束后由系统释放。</li>
</ol>
<p><strong>8.	负数在内存中是如何存储的？字符串在内存中是如何存储的？什么是大端序和小端序？</strong><br>负数先求相应正数、按位取反、再加1。字符串在内存中是以ASCII码存储的。大端序就是数据的高位字节存放在地址的低端，低位字节存放在地址的高端；小端序则是数据的高位字节存放在地址的高端，低位字节存放在地址的低端。</p>
<p><strong>9.	什么是内存对齐？为什么会有内存对齐？</strong> </p>
<ol>
<li>内存对齐就是将数据根据数据类型存放到以数据类型为倍数的地址处。而间隙处由无效数据补满。内存对齐通常出现在结构体中，最后结构体的大小是最大数据类型大小的整数倍。</li>
<li>内存对齐的原因：①硬件原因。某些平台只能在某些地址处取某些特定类型的数据。②内存对齐是内存规则分配的表现，能够提高CPU处理速率。</li>
</ol>
<p><strong>10.	CAN、I2C、UART、USB 2.0，它们分别需要几根线？每根线的功能是什么？如何连接？</strong></p>
<ol>
<li>CAN需要CAN-H和CAN-L两根线，通过两根线上的高低电平变化来实现数据的传输。CAN-H与CAN-L各自连接到CAN-H和CAN-L。</li>
<li>I2C需要时钟线(SCL)和数据线(SDA)，时钟线高低电平变化频率恒定，数据线通过高低电平跳变来实现数据的传输。两根线分别接到MCU的两个引脚，或SCL接SCL、SDA接SDA。</li>
<li>UART有三根线：TXD、RXD、GND。TXD用于发送数据，RXD用于接收数据，GND用于给信息传输的双方提供参考电平。发送方的TXD接到接收方RXD，RXD接到接收方TXD，GND相连。</li>
<li>USB2.0需要四根线：电源正极(VCC)、地线(GND)、负电压数据线(D-)、正电压数据线(D+)。两根数据线，两根电源线。每根线接收方与发送方一一对应连接。</li>
</ol>
<p><strong>11.	共模信号与差分信号的定义是什么？特点是什么？</strong></p>
<ol>
<li><p>共模信号是幅度相等、相位相同的信号。</p>
</li>
<li><p>差分信号就是差模信号，它是幅度相等，相位相反的信号。</p>
</li>
<li><p>在差分对中，差分信号被定义为两根单端信号的差值，共模信号指的是两根信号线上的平均值。</p>
</li>
</ol>
<p><strong>12.	模拟地与数字地为何需要隔离开并使用单点连接？</strong><br>这是在PCB设计中涉及到的问题。由于数字信号变化快，导致在数字地上会引起噪声，而模拟信号需要一个干净的地参考工作。若连在一起噪声会影响到模拟信号。单点连接即所有模拟地都拉出线，到同一点汇总，而两个模拟地之间都不再有另外的连接节点。这也是为了防止噪声干扰。</p>
<p><strong>13.	为何CAN总线需要加入终端电阻，不加会有什么后果？CAN通信拓扑结构为什么不能是环形？</strong><br>加入终端电阻是为了吸收信号反射及回波，提高抗干扰能力，提高信号质量。不加终端电阻会导致信号不稳、差分电压也会发生变化。环形拓扑结构可靠性差，若环上任意一个节点出现故障就会引起全网故障。而CAN总线正是具有多主控制，隔离故障单元的功能，若采用环形拓扑则使CAN不再是CAN。</p>

      
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<p>RT-Thread是一个集实时操作系统（RTOS）内核、中间件组件和开发者社区于一体的技术平台，由熊谱翔先生带领并集合开源社区力量开发而成，RT-Thread也是一个组件完整丰富、高度可伸缩、简易开发、超低功耗、高安全性的物联网操作系统。RT-Thread 具备一个 IoT OS平台所需的所有关键组件，例如GUI、网络协议栈、安全传输、低功耗组件等等。经过11年的累积发展，RT-Thread 已经拥有一个国内最大的嵌入式开源社区，同时被广泛应用于能源、车载、医疗、消费电子等多个行业，累积装机量超过4亿台，成为国人自主开发、国内最成熟稳定和装机量最大的开源RTOS。</p>
<p>RT-Thread 拥有良好的软件生态，支持市面上所有主流的编译工具如 GCC、Keil、IAR 等，工具链完善、友好，支持各类标准接口，如:POSIX、CMSIS、C++应用环境、Javascript 执行环境等，方便开发者移植各类应用程序。商用支持所有主流MCU架构，如 ARM,Cortex-M&#x2F;R&#x2F;A, MIPS, X86, Xtensa, C-Sky, RISC-V，几乎支持市场上所有主流的 MCU 和Wi-Fi 芯片。</p>
</blockquote>
<p>最近初步了解了RT-Thread操作系统，在此记录下其基础操作。下面附上RT-Thread相关网址：<br><a target="_blank" rel="noopener" href="https://www.rt-thread.org/">RT-Thread官网</a><br><a target="_blank" rel="noopener" href="https://www.rt-thread.org/document/site/">RT-Thread文档中心</a><br><a target="_blank" rel="noopener" href="https://www.rt-thread.org/page/video.html">RT-Thread教学视频中心</a></p>
<h2 id="初步认识"><a href="#初步认识" class="headerlink" title="初步认识"></a>初步认识</h2><ol>
<li><p>嵌入式操作系统是用来和上位机与硬件层对接的软件操作系统</p>
</li>
<li><p>RT-Thread 不仅是一个内核，还包含了众多组件，管理系统等</p>
</li>
</ol>
<h2 id="启动过程"><a href="#启动过程" class="headerlink" title="启动过程"></a>启动过程</h2><ol>
<li><p>systrmInit()</p>
</li>
<li><p>$Sub$$main()</p>
</li>
<li><p><strong>rtthreadread_startup</strong></p>
</li>
</ol>
<ul>
<li>board初始化即硬件初始化</li>
<li>rt_application_init();是用户任务创建函数</li>
<li>rt_system_scheduler_start();让rtthread跑起来</li>
<li>使用$Super $ $ test（）来替代原函数fun（），然后在$Sub $$ test（）函数中调用它，便可以在函数前后添加自定义代码了，这样便能够达到在完全对原函数不做修改的情况下，在前后添加自己的代码。</li>
</ul>
<ol start="4">
<li><p>rt_application_init()</p>
</li>
<li><p>main_thread_entry</p>
</li>
<li><p>$Super$$main(用户主函数)</p>
</li>
</ol>
<h2 id="动态内存堆的使用"><a href="#动态内存堆的使用" class="headerlink" title="动态内存堆的使用"></a>动态内存堆的使用</h2><ol>
<li><p>rt_system_heap_init()中，起始地址一般为ZI结束段，结束地址为片内地址的最后一段。将这一段分配出来的空间作为动态内存空间</p>
</li>
<li><p>RT-Thread中内存的使用和裸机状态下的区别不大，只需要换掉对应的API就可以</p>
</li>
<li><p>内存复位：申请到新的内存空间后，将内存空间清零，内存在之前可能是其他程序的数据存储区</p>
</li>
</ol>
<ul>
<li>P&#x3D;rt_malloc(10);<br>  如果申请成功<br>  rt_memset(p,0,10)</li>
</ul>
<ol start="4">
<li>内存泄漏：未释放已分配的动态内存</li>
</ol>
<ul>
<li>用rt_malloc申请后，用rt_free释放</li>
</ul>
<ol start="5">
<li><p>rt_realoc在已分配的内存块基础上重新分配内存块大小，变大就扩展，变小就会将后面的数据截断</p>
</li>
<li><p>rt——calloc(rt_size_t count,rt_size_t size)从内存堆中分配连续内存地址的多个内存块</p>
</li>
</ol>
<h2 id="线程的创建"><a href="#线程的创建" class="headerlink" title="线程的创建"></a>线程的创建</h2><h3 id="1-相关概念"><a href="#1-相关概念" class="headerlink" title="1.相关概念"></a>1.相关概念</h3><ul>
<li><p>线程代码（入口参数）</p>
<ul>
<li>无限循环，需要有让出内存的动作</li>
<li>顺序执行</li>
</ul>
</li>
<li><p>线程控制块</p>
<ul>
<li>用于管理线程的一个数据结构，会存放线程的一些信息</li>
</ul>
</li>
<li><p>线程堆栈</p>
<ul>
<li>每个线程有独立的栈空间，线程切换时会将线程的上下文（线程执行时的环境）保存在线程栈中</li>
</ul>
</li>
</ul>
<h3 id="2-线程创建"><a href="#2-线程创建" class="headerlink" title="2.线程创建"></a>2.线程创建</h3><ul>
<li><p>创建线程</p>
<ul>
<li><p>rt_thread_init（创建的是静态线程，需要你告诉堆栈起始地址）</p>
<ul>
<li>const char  *name为线程名字</li>
</ul>
</li>
</ul>
</li>
</ul>
<p>void *parameter为线程代码<br>*parameter为线程（入口）参数</p>
<pre><code>- rt_thread_create（创建的是动态线程，系统自动为你分配运行空间）
</code></pre>
<ul>
<li><p>启动线程</p>
<ul>
<li>tr_thread_startup之后线程才受调度</li>
</ul>
</li>
</ul>
<h3 id="3-静态线程和动态线程"><a href="#3-静态线程和动态线程" class="headerlink" title="3.静态线程和动态线程"></a>3.静态线程和动态线程</h3><ul>
<li><p>相关资源分配形式</p>
</li>
<li><p>运行效率</p>
<ul>
<li>没有外扩RAM，效率相同</li>
<li>有外扩RAM，如果动态线程是在外扩RAM中被分配的话，那它的运行速度就会下降，因为片内RAM运行速度大于片外RAM</li>
</ul>
</li>
</ul>
<h2 id="创建LED流水灯线程"><a href="#创建LED流水灯线程" class="headerlink" title="创建LED流水灯线程"></a>创建LED流水灯线程</h2><ol>
<li><p>在thread_sample中创建线程函数</p>
</li>
<li><p>创建入口函数，必须要有让出CPU的操作，比如流水灯中的延时</p>
</li>
<li><p>将创建的线程函数放入main中</p>
</li>
<li><p>怎样分配栈空间大小</p>
</li>
</ol>
<ul>
<li>在调试界面下，用list_thread命令，查看当前所有线程状态，max used百分比为线程最大使用了你分配的栈空间，可以通过修改栈空间大小，一般将线程栈最大使用量设置为70%</li>
</ul>
<ol start="5">
<li><strong>RT-Thread移植后与裸机 LED 闪烁应用代码的不同</strong></li>
</ol>
<ul>
<li>延时函数不同： RT-Thread 提供的 rt_thread_mdelay() 函数可以引起操作系统进行调度，当调用该函数进行延时时，本线程将不占用 CPU，调度器切换到系统的其他线程开始运行。而裸机的 delay 函数是一直占用 CPU 运行的。</li>
<li>初始化系统时钟的位置不同：移植好 RT-Thread Nano 之后，不需要再在 main() 中做相应的系统配置（如 hal 初始化、时钟初始化等），这是因为 RT-Thread 在系统启动时，已经做好了系统时钟初始化等的配置，这在上一小节 “系统时钟配置” 中有讲解</li>
</ul>

      
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